Design and Simulation of an Optimized 8-Bit Hybrid Adder using Xilinx Vivado

Efficient arithmetic units are crucial components of a digital system, particularly Digital Signal Processors (DSPs) and also digital circuits that require optimized use of power, area and other performance parameters. This paper presents the design and simulation of architectures of pipelined and non-pipelined 8-bit hybrid adders using Xilinx Vivado Design Suite. The proposed architectures combine the speed of a Carry Select Adder (CSLA), and the area efficiency of a Carry Skip Adder (CSKA) to achieve an optimal balance in the performance parameters of both the standalone adders. The design is modeled using Verilog HDL and verified through functional simulation and post-RTL synthesis. The results demonstrate that the hybrid developed achieves a significant improvement in performance parameters such as power consumption, utilization and timing analysis, compared to each individual adders, making it a suitable design for energy efficient and high-speed circuit.