Reconfigurable Memristor-Enhanced Circuit Design for Neural Network Applications

Deep neural networks (DNNs) deployed on edge devices face critical challenges, including high power consumption, latency due to analog-to-digital (ADC) and digital-to-analog (DAC) conversions, and memory bottlenecks inherent in conventional architectures. We propose a novel reconfigurable memristor-enhanced circuit design methodology for energyefficient neural network execution that minimizes reliance on power-intensive ADC/DAC operations. Our approach employs a lightweight convolutional neural network (CNN) built with depthwise separable convolutions and two novel memristor-inspired activation functions— RSign and RPReLU. We implement a two-phase hardware-aware training strategy and validate the analog characteristics of the RSign circuit using LTspice simulations, confirming functional correctness and low-power operation. The trained models are deployed on a PYNQZ2 FPGA board, achieving 90.0% classification accuracy on CIFAR-10 test images with an average inference time of 103.2 ms per image and energy consumption of 0.1070 J per image at 2.8 W. The system demonstrates strong noise resilience, maintaining 80.0% accuracy under Gaussian input noise (σ = 0.02–0.10). Additional evaluations confirm efficient performance on other datasets, including 88% accuracy on MNIST at 74.54 mW and 82% accuracy on CIFAR- 10 at 97.8 mW. These results highlight substantial improvements in energy efficiency over conventional approaches, offering a practical pathway toward sustainable, high-performance AI deployment on resource-constrained edge devices in domains such as IoT, autonomous systems, medical diagnostics, and smart surveillance.