Implementation and Performance Analysis of Various Scan Compression Techniques

In today’s scenario, the number of transistors on a chip has increased t o several millions. If number of scannable flops also increases in design; FULL-SCAN test patterns are very costly to use. They also require more memory to store the test data on Automatic test equipment and takes longer time to test. In this work, we have investigated two different scan compression techniques to compress the test data volume and reduce the testing time. First technique uses a Broadcast decompressor and second technique uses an Embedded Deterministic Test (EDT) logic. The experimental results show that how scan compression is effective than the traditional full-scan. For the second technique, we compare the performance parameters of same design having different scan compression ratio. Here, w e observed that the design having more compression ratio requires more test pattern to detect t h e faul t . So, we can say that, there must be some optimum value of compression ratio for a particular design to take maximum advantages of scan compression.