Comparative Analysis of Open-Source EDA Tool for VLSI Physical Design

Open-source EDA tools are becoming very popular nowadays and they are also becoming more efficient. Academic researchers can use these open-source EDA tools which are free of cost and still give the idea about the whole chip design flow. These open-source EDA tools can also be used for real chip tap out so we can also manufacture a chip with the layout made with such tools. Commercial tools require very high license costs and are used in industries for high efficiency. The arithmetic and Logic Unit is the fundamental building block in any processor which performs arithmetic and logical operations. ALU is widely used for signal processing tasks where lots of additions and multiplications need to be performed at very high speed and also in communication-related applications. In this paper, the whole flow of chip design is performed on 8-bit ALU with both open-source tools that are Qflow and commercial tool that is Cadence Encounter. The RTL design is first written in Verilog and also functionally verified. Then Synthesis is done which converts RTL code into a gate-level netlist. Then different physical design steps like partitioning, floorplanning, power planning, placement, CTS, routing, timing closure are performed. After STA, LVS, DRC, the final layout is generated that is GDS-II file which can be given for tape out. The 180nm technology node is used in the physical design. With so many advantages of open-source tools, to know how efficient they are, design is done in Qflow and Cadence Encounter. Results are compared based on area, speed, and power which are the most important parameters in VLSI design. From the result, it can be seen that the area requires in design made with Qflow is almost 4 times larger than the design made with Cadence Encounter. Power required for design with Qflow is 25 times higher than design with Cadence Encounter.