An Analysis in to CMOS 1-Trit Ternary Full-Adder Technology

The paper presents an overview of work done in VLSI CMOS (complementary metal oxide semiconductor) during the previous two decades on several types of adders, including ternary adders and others. The adders and designers devised effective methods for presenting their ideas. To provide context for the study, a variety of articles are reviewed and analysed. With the growing demand for battery operated, mobile, efficient systems, application-based processing is becoming more common as opposed to old-school technology-based gadgets. The biggest problem when dealing with high-speed functioning devices is power waste. As device transistor sizes shrink, we face the challenge of increasing the density of a single integrated circuit. Due to increased manufacturing complexity as well as other concerns such as capacitance and scaling constraints, high connection complexity makes VLSI/ ULSI extremely challenging. When compared to binary adders, ternary adders function efficient better in terms of information transmission. The quaternary data transmission rate is much higher than the binary and ternary data transmission rates.