High Throughput on-the-fly Implementation for AES

This paper presents the outcome of our implementation of On-The-Fly based Rolled architecture for all key size AES on a TSMC 0.18μm technology. The architecture performs Encryption and Decryption both. We have employed Composite Field arithmetic for computations under SubstituteByte operations with design decisions for selection of appropriate polynomials to achieve least critical path delays. We have achieved a throughput of 2.33Gbps and one of the best throughput/area of 192 Mbps/K-gates. The whole design could fit into 0.19mm2 area with power consumption of 19.263mW. The key expansion unit is designed for 128, 192 as well as 256-bit round keys. Critical path delay analysis for the whole design was performed to achieve minimum inter path delay difference so as to reduce unnecessary transitions (Dynamic Hazards) in the combinational circuit paths, which helped us in clocking the design at 182MHz.