Design and Physical Implementation of Custom RISCV Processor from RTL to GDSII

This paper describes the details of a custom RISC-V processor design from the Register Transfer Level (RTL) stage to the final GDSII layout. It is capable of supporting single-precision R-type (Register) and F-type (floating-point) instructions. On the R-type side, the processor can perform the following operations: ADD (addition), SUB (subtraction), AND (bitwise AND), OR (bitwise OR), XOR (bitwise XOR), SLL (shift left logical), SLT (set less than), SLTU (set less than unsigned), SRL (shift right logical), and SRA (shift right arithmetic). In addition to these F-type operations: ADD, SUB, MUL (multiplication), DIV (division), MAX (maximum), MIN (minimum), LEQ (less than or equal), EQ (equal), and LT (less than). Major blocks such as an Arithmetic Logic Unit (ALU), decoder, and memory are wired together, with a data selector multiplexer regulating ALU operations and memory bank. The floating-point instructions extend the range of numerical calculations, thus providing a faster solution for the scientific simulations and graphic processing applications. The implementation is a full custom design and the stages of the development have been documented as follows: The design has been verified with the help of Cadence SimVision, synthesized using Cadence Genus, Physical design accomplished by using Cadence Innovus.