Optimized Design and Analysis of Low Power 32-Bit Reversible Adder

There is a great demand for low power design in the emerging computing era. Reversible logic emerges as perspective design that is useful in power-constrained environments, minimizes the information loss and energy dissipation unlike conventional irreversible logic. This work explores the low-energy design and performance optimization of a 32-bit reversible adder using a 45 nm full-custom approach. The design process starts with implementing fundamental reversible logic elements namely the Peres, Toffoli, Fredkin, and Feynman gates and later enhances them using transmission-gate-based optimization. The design adopts a modular approach by creating a one-bit reversible addition module and cascading multiple units to construct a 32-bit reversible carry-based adder, while minimizing the generated garbage outputs. The optimized reversible addition module enhances the standard design by lowering both area and power consumption. A 1-bit reversible adder design shows 20.2% power savings and 8.8% speed improvement over standard CMOS. While for the 32-bit adder, power drops 30.3% and delay improvement of 4.8% is achieved over conventional design, demonstrating efficiency for low power applications. The 32-bit reversible adder is designed to form as a fundamental element for reversible ALU used in reversible processor. The results demonstrate low power, reduced transistor count, scalable high speed reversible adder making it a promising approach for emerging computing paradigms.