AXI4 Hybrid Round-Robin Arbiter with FIFO for Six Masters

This paper presents the design and simulation of an efficient AXI4 Hybrid Round- Robin Arbiter with FIFO support, tailored for systems featuring six master interfaces. Efficient communication between multiple master devices and a shared slave is a fundamental requirement in System-on-Chip (SoC) design. The Advanced extensible Interface (AXI4) protocol, part of the AMBA specification, enables high-throughput and low-latency communication through multiple outstanding transactions. In multi-master configurations, arbitration becomes essential to manage concurrent access requests. This paper presents a simulation-based design of a Hybrid Round- Robin Arbiter with integrated FIFO queues for six AXI4 master interfaces. The hybrid arbitration approach combines round-robin fairness with dynamic readiness checking to optimize bus utilization and prevent starvation. FIFO buffers further enhance system performance by decoupling master and slave timing. The design is implemented in Verilog HDL and verified using simulation tools to ensure functional correctness, transaction integrity, and fair access scheduling. The proposed arbiter effectively handles contention and ensures smooth data flow in AXI4-based systems, making it ideal for use in simulation and verification environments.