Efficient I2C Protocol Implementation for Digital Control Interface using FPGA

The Inter-Integrated Circuit (I²C) protocol is widely adopted in embedded and digital control systems where compact, reliable, and low-power communication is required. To support efficient system integration, this work presents a lightweight I²C slave controller implemented in VHDL and optimized for FPGA platforms. The design incorporates 7-bit addressing, accurate START/STOP detection, synchronized read/write transfers, and ACK/NACK response handling. A centralized finite state machine (FSM) governs communication flow, while an optional debouncing mechanism on SCL and SDA inputs improves noise resilience with negligible resource overhead. Functional validation through simulation verified correct operation across diverse cases, including address mismatches, repeated reads, and asynchronous STOP events. Hardware synthesis on a Xilinx Zynq-7000 device confirmed the compactness of the design, requiring only 53 LUTs and 22 registers. The proposed controller thus delivers protocol compliance, low resource utilization, and FPGA readiness, making it suitable for embedded sensor modules and peripheral control applications.