A Low Power Dual-CLCG for Pseudorandom Bit Generation

Pseudo Random Bit Generator (PRBG) is a need factor for getting data through transmission in different cryptographic applications. In the normal existing Pseudo random bit generation systems like Linear Feedback Shift Register (LFSR), Linear Congruential Generator (LCG), Coupled LCG (CLCG), and Dual Coupled LCG (Dual-CLCG), the last ends up being more secure. This technique relies upon correlations that causes pseudorandom bit generation at a non-uniform stretch. The drawbacks listed for this technique are excessive memory usage, high-initial clock latency, failing to grasp the foremost length sequence. In this paper we have proposed a Modified Dual-CLCG technique at a uniform clock rate to produce pseudorandom number. The tale commitment of the arranged PRBG method is to have pseudorandom bit with low power. The present proposed architecture offers significant improvement in terms of power and speed in comparison to other reported architectures. Architecture for LCG is compared with different devices so that Artix 7 shows least power having a value of 0.042W. The execution of PRBG strategy is simulated utilizing VHDL and is reconfigurable utilizing Artix 7 FPGA board.