RTL to GDSII Implementation of UART Communication Over RSA Algorithm using 90nm Technology

In this work, we describe the design and implementation of an 8-bit Universal Asynchronous Receiver-Transmitter (UART) configured for a baud rate of 9600. The primary goal was to create a UART architecture that minimizes both silicon area and power usage, achieving an area of 546.482 μm² with 66 instances and a power consumption of 17.299 μW(Post CTS). The design flow covered all stages from RTL coding to GDSII generation, ensuring reliable performance and smooth integration into larger systemsAn important feature of the design is the addition of input/output (I/O) pads, which improve signal integrity and simplify connectivity with external modules. This is especially beneficial for ensuring robust data transfer in conditions where signal interference may occur. The proposed approach maintains a careful balance between power efficiency and area optimization, making the UART suitable for use in embedded platforms and communication systems. The implementation was carried out using the 90nm technology library. Synthesis confirmed that the design achieves minimal area utilization while keeping power efficiency at a competitive level. Functional verification was performed through simulations in Xilinx Vivado, while synthesis was handled in Cadence Genus. Floorplanning was carried out in Cadence Innovus, followed by Design Rule Checking (DRC) and Layout Versus Schematic (LVS). These steps ensured compliance with fabrication standards and made the design tape-out ready.