Power Efficient Memory based Transistor-Memristor with CMOS Configuration Hybrid Mode Circuits for Future Neuromorphic Computation

This work explores the design of essential arithmetic blocks for digital logic circuits such as encoder, decoder, full adder, multiplexer, and multiplier using a hybrid CMOS– Memristor approach. The aim is to create more compact and energy-efficient alternatives to traditional CMOS designs by taking advantage of the memristor’s programmable resistance. Each circuit has been built and simulated using LT-Spice to study its functionality, power efficiency, and performance. The results show that incorporating hybrid approach of CMOS with memristors significantly reduces the number of components and power usage while maintaining reliable operation. This work highlights the potential of memristor-based logic as a promising direction for future low-power and scalable digital systems. About 98% of power optimization and Hybrid mode arithmetic circuits show optimization up to 98% compared to CMOS technology.