FPGA-based Implementation of Dark Channel Prior for Image Dehazing

Image degradation due to atmospheric haze significantly impairs visual quality and the performance of computer vision systems. This paper presents a Verilog-based hardware system for image dehazing, primarily implementing the Dark Channel Prior (DCP) algorithm. The system architecture is designed for Field-Programmable Gate Array (FPGA) deployment, emphasizing a pipelined approach for high throughput. Key components include modules for dark channel calculation, atmospheric light estimation, transmission map estimation, and guided filter-based transmission map refinement. An optional processing path incorporating YCbCr colour space conversion is included for targeted brightness enhancement of the dehazed image. This paper details the theoretical underpinnings of the implemented algorithms, the specifics of the hardware architecture including Verilog module design, and a comprehensive performance evaluation. Results demonstrate the system's capability for efficient haze removal, with analysis of processing speed, FPGA resource utilization, power consumption, and quantitative dehazing quality.