RISC-V based Cryptographic ECC-AES Hybrid Core for Secure Communications

In the era of pervasive connectivity, secure communication has become a fundamental requirement in embedded system design. The growing number of resourceconstrained devices demands lightweight yet efficient cryptographic engines that balance performance, security, and scalability. This paper presents the design and simulation of a RISC-V–based processing platform integrated with a hybrid Elliptic Curve Cryptography (ECC) and Advanced Encryption Standard (AES) engine. Implemented in Verilog HDL, the architecture comprises a RISC-V CPU, an ECC module for 256-bit key generation, and an AES encryption/decryption core. The ECC-generated public key (Qx) is directly employed as the AES key, while a memory-mapped interface enables seamless communication between the processor and cryptographic modules. The CPU executes preloaded instructions to emulate arithmetic and memory operations, thereby producing realistic switching activity for performance and power evaluation. Simulation results validate the functional correctness of the platform. Encryption of a single plaintext required 36 cycles in both standalone and integrated configurations. For multiple plaintexts, the standalone system required 144 cycles for five blocks, whereas the integrated platform achieved the same in 124 cycles, yielding a 13.89% reduction in average cycles per block. Power analysis showed 164 mW for the standalone design and 198 mW for the integrated version. The proposed RISC-V–integrated ECC–AES platform thus achieves cycle efficiency with modest power overhead, making it a scalable and modular hardware solution for secure embedded applications.