Comparative Analysis of Ternary Logic Gates using CMOS and CNFET

The limitations inherent in traditional binary logic systems, particularly regarding interconnect complexity and energy efficiency, have spurred increased interest in multi-valued logic (MVL), with a specific focus on ternary logic due to its capacity for enhanced information density and computational efficiency. The paper presents a comparative analysis of fundamental ternary logic gates is by using unbalanced ternary logic (0, 1, 2) Using multithreshold in both conventional CMOS and innovative Carbon Nanotube Field-Effect Transistor (CNFET) technology. Utilizing the Cadence Virtuoso design tool, various ternary gates, including the ternary inverter, NAND, NOR gate were designed and simulated. Key performance metrics such as power dissipation and delay were Calculated.