Design of 4-Bit Flash ADC using 28nm Technology in Cadence Virtuoso

The Flash analog to digital Converters (ADC) are known for their high-speed conversion and simple architecture, making them ideal for time-critical applications. This article provides the schematic-level design and simulation of a 4-bit Flash ADC in 28 nm CMOS technology in Cadence Virtuoso. The design includes a resistor ladder, an array of comparators made from pre-amplifier based comparators, and a thermometer encoder. The purpose of using pre-amplifier stages in the comparator array is to improve the sensitivity and reduce the offset of the comparator, ultimately enhancing speed and accuracy. This work shows that preamplifier based comparator designs have a significant improvement for their application to ADCs in advanced CMOS nodes, which may be useful for creating low-complexity and lowpower analog-to-digital interfaces. Each sub-block was simulated, in isolation, to verify its working functionality. The test results show that the design operates at a clock frequency of 80 MHz, consuming a total power of 508.6 μW, which is most effective for low-power, high-speed applications.