A 32-Bit Altered Partial Product Multiplier for Low- Power and Low-Area Applications

The concept of approximate computing gives scope for applications in various areas. Signal processing and image processing applications doesn’t require exact arithmetic designs. The outputs of their huge computational units provide error tolerance where approximate computational blocks can be made use of. Computational blocks include inexact adders and multipliers at the basic level. Approximate computing develops simplified units saving complexity and power consumption compared with the exact designs. An advanced multiplier design is introduced in the paper which makes use of the concept of altered partial products using two different signals propagate and generate to replace the original partial products. Two sorts of 32-bit multipliers are explored in the paper. The 32- bit multipliers implementation is done in Verilog, simulation is performed using the Cadence Native Compiler and synthesis is accomplished using Cadence Encounter making use of 45nm technology.