Realization of Verilog-based Low Power Universal Asynchronous Receiver or Transmitter (UART) Communication Protocol

This article is a thorough research paper on the low power techniques using Universal Asynchronous Receiver Transmitter (UART) communication protocol with the goal of educating pertinent personnel about its applications and guiding principles while also advancing UART research's advancement. In terms of digital communication, Serial connections between distant embedded systems can be established via UART. For low-cost and low-speed applications, this protocol is utilized to attain resilience amid permissible frequency variations between systems. This study examines whether clock gating and other low power strategies may be effectively utilized in a UART receiver to minimize clock power. The suggested clock gating technique minimizes needless clock transition of operative blocks in the inactive state makes certain that the dynamic power in the operational state does not adversely impact the design.