Implantation of 1X3 Router in FPGA

In this paper, we expound the design and implementation of a 1x3 router based on FPGA for communication and embedded systems. One of router's three outputs is routed to from an 8-bit input data stream, selected by a con-figurable 2-bit select signal allowing for greater flexibility and determinism in data distribution. The specific work is described in a synthesizable Verilog HDL to evaluate the resource utilization and performance on intel FPGA (MAX 10 FAMILY) The functional simulations of router prove the correct functionality for different input data. The synthesis results show that it occu-pies fewer resources, and the timing analysis proves its high speed, which is capable of operational in real-time applications.