Reversible Logic based Modified Design of AESCBC Mode

Advanced encryption standard (AES) is the most widely used secure symmetric algorithm nowadays. AES is a block cipher, in which different operations are performed on group of bits called a block. In order to encrypt N number of blocks, different modes of operations have been proposed. There are five modes of operations of AES proposed namely, Electronic Code Book(ECB) ,Cipher Block Chaining(CBC), Cipher Feedback(CFB),Output Feedback(OFB) and Counter (CTR) mode. Based on the analysis, CBC mode of operation is found to be the best. In CBC mode initialization vector (IV) is used. Initialization vector should be same as that of size of block. IV is XORed with the first plaintext block. The XORed result is encrypted with the key. The encrypted result (ciphertext) is used as IV to the next proceeding blocks. CBC performs operations on blocks of standard size (i.e, 128). We identified that existing CBC requires more computational time as it operates on n-block plaintexts and also more hardware. So we tried to modify the existing CBC in order to reduce the hardware used, computational time and also to improve the security by using equal key and message size. Shannon’s theorem states that a one-onone relationship between each message bit to each key bit (hence both key and message length equal) would give the best security. To improve the security of the original CBC mode, message size is increased from standard block size of 128 bits to 256 bits and key size is made as equal as the message block size. We get more security by the use of larger key size and the increased throughput from the larger input block size compared to original AES of 128 bits. In our proposed work IV and XOR operation is not used. The first stage ciphertext is used as key for the next stage and so on. We designed and simulated 512 bit encryption using both already existing CBC and our proposed CBC. In the modified CBC 512 bit plaintext is divided into two blocks of each 256 bits instead of four blocks of each 128 as in existing CBC. The hardware required and delay of both are compared with existing work and found to be less. In order to combat power attacks in conventional algorithm, reversible logic is used to implement the design.