Performance Analysis of AES-128 Bits, 192 Bits and 256 Bits using Reversible Logic

The reduction of power dissipation remains one of the major goals in the VLSI circuit design for many years. Classical circuits shows power dissipation for every bit lost in computation. But, reversible circuits do not dissipate power as no loss of bits in the information. It has an application in diverse fields like low power CMOS design, optical communication, cryptography, quantum computing and nanotechnology. Cryptography is a vital part of securing private data and preventing it from being stolen. Cryptography algorithms are either symmetric or asymmetric depending type of secret keys used. Among existing symmetric cryptography algorithms, AES(Advanced Encryption Standard) widely used as it is non fiestal, symmetric, faster with good security. One of the important feature of AES algorithm is that, it supports both hardware and software implementation, which is not true in other algorithms. But AES do have attacks like brute force attack and side channel attack, which occurs mainly due to power dissipation and can be well addressed by using reversible logic as it gives zero internal power dissipation. The paper is intended to design AES with different key lengths (128 bit, 192 and 256) to increase the security level using reversible gates. The AES algorithm of 128, 192, 256 bits key length for cryptographic procedure has been simulated and verified on FPGA Virtex 5 ML505 board using Xilinx chipscope. Proposed 128bit AES uses less number of garbage, gates , ancilla inputs and reduced quantum cost in comparison with existing work (only for 128bit). Also design of 192bit and 256bit AES is proposed and analyzed for performance parameters, but no such work found in literature for comparison using reversible logic. Power and time consumed are also compared for different key lengths in this paper.