Design a Vedic Multiplier using Xilinx Vivado

This research investigates the usage of traditional Indian Vedic multiplier, array multiplier, and Wallace tree multiplier. The main focus of high- speed processors is to minimize power consumption and processing times, which is effectively demonstrated by the Indian Vedic multiplier. The implementation of the design utilizes Verilog, a hardware description language, and the testing phase is carried out using the Modelism simulator. The study compares the performance of these multipliers. The outcomes emphasize that when a ripple carry adder is employed, the Indian Vedic multiplier outperforms both in terms of power consumption and time delays