Design and Implementation of LVCMOS18 I/O Buffer

The VLSI integration technology is growing at a rapid rate. As a result, there is a need for smart devices with high performance operation. This plays a vital role in the consumer industry at larger scale in day-to-day life. To enhance performance of the new devices, more robust interfacing standards are required. Hence, the proposed paper discusses the design of the I/O standard LVCMOS18 buffer with 0.9V interface at the transmitter with an operating frequency of 150 MHz. The interface I/O design uses 90nm GPDK technology and is tested with various process corners with 4 mA current drive capability. The results obtained are found to be encouraging for all the design specifications of LVCMOS 18 I/O standard for the transmitter