Formal Vs Simulation based Verification on Receiver Training Sequence Block of USB3.2 Controller

The constant evolution of high-speed digital inter- faces has created a demand for robust and reliable designs. As a key component in ensuring reliable data transfer, receiver training sequence modules play a critical role in high-speed serial communication protocols like USB (Universal Serial Bus). Formal verification and Simulation based verification are two different methods for verifying the correctness of any digital design. The Simulation based verification checks the correctness of the design through the simulation of the design. It includes building of test bench architecture using System Verilog (SV) and Universal Verification Methodology (UVM), whereas Formal verification is a mathematical approach of verifying the design exhaustively. This paper gives a comparative analysis of a design using the two different verification methods. The block subjected for the verification has been taken from the Universal Serial Bus 3.2 (USB) controller. Using formal verification two corner case bugs were found and fixed at the early stage of the project and 100% code coverage is achieved