Chip Variations in Fabrication: Causes, Effects, and Mitigation Techniques for Enhanced Performance

In the present-day, the chip industry stands as the economic cornerstone of the modern world. The primary objective of the VLSI semiconductor industry is to attain optimal performance while minimizing costs and power consumption. With rising competition among semiconductor companies, there has been a significant focus on reducing MOSFET size and adopting emerging technology nodes. However, these new nodes may not be fully optimized for high yield in mass production. The need of the hour is to devise a technique that can enhance yield in the semiconductor field, striking a balance between quality and functionality. The quality of results (QoR) for current Application-Specific Integrated Circuit (ASIC) methods has been observed to be significantly influenced by variations. Post physical design and sign-off, the chip is sent for fabrication, where it is susceptible to chip variations, broadly categorized as "global process variation" and "on-chip variation". Neglecting chip variations during the design phase can lead to timing violations and power failures. During this work, chip variations are briefly addressed with possible aids