Ternary Adder and Multiplier Design using GNRFETs

The ternary logic systems offer significant improvements in terms of bandwidth, operation, interconnect length and so on compared to two-valued logic. This work presents the proposal of novel digital circuits with ternary combination that decrease delay at lower power VLSI(Very Large Scale Integration) devices. The complicated circuits likemultiplier and adder can be developed using GNRFET (Graphene Nano Ribbon Field Effect Transistor) without decoders and encoders circuits.The ternary adder, multiplier circuits based on GNRFET can be created and emulated utilizing the HSPICE (Hewlett Simulation Program with Integrated Circuit Emphasis) software. Also, it is examined the proposed circuits delay, EDP (Energy Delay Product), PDP (Power Delay Product) and Energy respectively. In order to show proposed design efficacy, performances of the proposed adder and multiplier designs are compared with CNTFET(Carbon Nanotube Field Effect Transistor)-based adder and multiplier designs