Exploring Full Adder Design Options for 90nm Technology Node: An In-depth Performance Analysis

This study presents a comprehensive examination of the various full adder circuit designs, which form the core of many high computational arithmetic logic circuits in low voltage low power VLSI designs. Any researcher's ultimate objective is to increase speed and efficiency while minimizing the circuit's need for space by optimizing its performance. In this paper, the benefits and drawbacks of several design techniques employed in the development of the full adder have been examined. Various state-of-the-art full adders at the 90nm technology node have also been compared and analyzed