Design and Synthesizing of Floating Point Adder and Multiplier using Cadence RTL Compiler

Floating point arithmetic is widely used in many areas. IEEE Standard 754 floating point is the most common representation today for real numbers on computers. IEEE standards specify a set of floating-point formats for single precision and double precision. The representation of very large or very small values, is carried out using the IEEE-754 floatingpoint standard. This work intends to develop an Verilog implementation of a floating-point arithmetic unit which can perform addition, subtraction and multiplication operations on 32- bit operands using IEEE 754-2008 representations. Low power consumption and smaller area are some of the most important criteria for the fabrication high performance systems. The algorithms will be model in Verilog and synthesized using Cadence RTL complier using Cadence 45nm GPDK.