Optimised DFT Architecture through Scan based Design

In this paper, an Optimized DFT architecture through Scan based design is proposed, where an efficient Low Power test pattern generator is used to verify any real time Design Under Test (DUT) module using Functional and Structural testing. The MUX based parallel data input Linear Shift Feedback Register along with gray code converter architecture reduces the initial latency in turn increasing the speed of architecture. Further, the generation of test patterns using characteristic equation optimizes the memory required and also minimizes the complexity of overall verification techniques in terms of hardware utilizations. The intended LFSR saves power by 14 % which is generated through SAIF file using synopsis tool and Tessent tool .DFT flow is adopted to do Scan insertion and ATPG and able to achieve fault coverage by 97% for one of the design chosen .it is compared with prevailing techniques to prove the efficiency in terms of Power utilizations and Fault Coverage.