Implementation and Performance Analysis of Boundary Scan Testing

Testing refers to the process of checking the accuracy of a device manufactured using specific test stimuli and observing the output signals. Boundary Scan is a technique of testing interconnections to printed circuit boards or small blocks contained in an IC. The boundary scan circuitry is included in the ICs input and the test is performed by supplying test patterns. The proposed work is about the study and analyzing recently reported boundary scan testing techniques. This work mainly focuses on IEEE Stds 1149.1 and 1500 because these are widely used nowadays as compared to other standards. In the proposed work, boundary scan testing is carried out by considering SoC design as core logic. Some issues are analyzed in proposed SoC testing and an appropriate solution is provided. The effectiveness of this method is analyzed by measuring fault coverage and speed of execution for the design.t