Design and Analysis of 60ghz Frequency Divider using MCML Logic

High speed and low power are the main challenges in modern VLSI design. The proposed paper presents swift frequency divider circuit using MCML (MOS Current Mode Logic). The divider operates up to 60GHZ clock frequency. The implementation is carried by using 45nm cadence virtuoso tool. The presented logic consumes 2.5mW from 1.2V supply. The phase noise of the proposed frequency divider is 150dBc/Hz at 60GHz offset.