Abstract

Clock gating is extremely useful for decreasing the power wasted by digital circuits. This paper proposes a new and innovative method of look ahead clock gating. It avoids and eliminates the drawbacks of the previously used methods. The existing systems for clock gating are synthesis base clock gating, data driven clock gating and clock gating on auto gated flip flops but all these techniques had a number of disadvantages. This project deals with the elimination of the drawbacks in the existing system Look-Ahead Clock Gating (LACG), combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time and further DETFF and dual pulse generator are used to increase performance.