Abstract

From few decades Coordinate Rotation for Digital Computers (CORDIC) algorithm has received attention from academic and industry because of its applications in DSP, biomedical processing, neural networks, MIMO and many more. It is a repetitive algorithm, which involves shift and addition operations, for hardware understanding of basic uncomplicated functions. CORDIC is used as a fundamental block for building a variety of single chip solutions; aspects which are critical and need of consideration are high speed, low power and area, to achieve realistic on the whole performance. In this paper we will discuss about Parallel and Serial implementation, folded and unfolded implementation and IQ-Math and FP-Math CORDIC architectures on FPGA. In-depth evaluation of different architectures are presented, which makes available a first order information to designers who looks out for either advance development of performance or choice of rotational CORDIC for a precise function.