Abstract

Phase Locked Loop (PLL) is a control system used for synchronization to achieve same frequency. It is used in clock generation, clock recovery. In this paper, a 1.1 V, operating at 400MHz phase-locked loop implemented in 45 nm CMOS technology using standard cell i.e phase frequency detector uses D Flip-Flop and NAND gate using standard cell .The output from the PFD is connected to the low pass filter which is designed using capacitor and resistor in which the overall area of the circuit is reduced. The loop filter is passive for less area. Phase lock loop produces an output frequency match with the frequency of an input signal. The designed PLL has the operating frequency of 1.6 GHz. The voltage controlled oscillator used is current starved voltage controlled .For low power the PFD uses D Flip-Flop which produces low power Phase Locked Loop. The voltage controlled oscillator produces output frequency and high gain. Some of the performance parameters to be considered are locking range , tracking range .Higher bandwidth is provided to prevent noise and passive loop filter for stability .Since today’s communication media uses phase locked loop in GHz range .The work focuses on reconstruction of PLL in GHz range using standard cell layout design.