Fast Architectures for Arithmetic Operations via
Vedic Sutras
Journal:
GRENZE International Journal of Engineering and Technology
Authors:
Thippeswamy K H
Volume:
3
Issue:
3
Grenze ID:
01.GIJET.3.3.96
Pages:
138-141
Abstract
The “Time” and “area” are the two important constraints in any processor IC
design. In any digital design process, these two constraints play a contradictory role and
thus there exists a trade-off between them. Optimizing the two said constraints is a
challenging task in the design process.
The arithmetic operations {+, - ,* ()2 } have been found to possess redundancy when
implemented in conventional way. Based upon simulation using Vedic mathematics,
resource utilization and time delay will reduce by more than 50% to 75% for multiplication
and squaring with increase in number of digits.
This paper presents Vedic mathematical based arithmetic operation implementation and
the results have been presented using Urdhva Tiryagbhyam, Dvandva Yoga sutras.