Implementation and Determining Low Power Analysis of Various Structures of SRAM Cell

Journal: GRENZE International Journal of Engineering and Technology
Authors: Lakshmidevi.T.R
Volume: 3 Issue: 3
Grenze ID: 01.GIJET.3.3.66 Pages: 78-82

Abstract

The Reduction of the channel length due to scaling increases the leakage current resulting in a major contribution to the static power dissipation and for stability of the SRAM cell good noise margin is required so noise margin is the most important parameter for memory design. The higher noise margin of the cell confirms the high-speed of SRAM cell. In this work, SRAM Cell with six transistors is being proposed to reduce the static hence total power dissipation. When compared to the conventional 6T SRAM, 7T, 8T, 9T, 10T_SRAM cell and the proposed modified 6T SRAM with stack operation shows a significant reduction in the gate leakage current, static and total power dissipation while produce higher stability. In the technique employed for the proposed SRAM cell, the aim is to reduce the leakage power, leakage current and improve the read behavior of the different SRAM cell structure for 64 bit using cadence tool at 180nm technology while keeping the read and write access time and the power as low as possible analyzed by normal simulation and mote carlo simulation.

<< BACK

GIJET