Enhancement of Smart Grid Performance through Logic based Fault Tolerant MPSoC

Conference: Fifth International Conference on Advances in Electrical Measurements and Instrumentation Engineerin
Author(s): D.Vijayakumar, V.Malathi Year: 2016
Grenze ID: 02.EMIE.2016.5.1 Page: 25-34


Sustainable energy is the energy production without compromising the energy production for the future generations. This paper presents the picture of today’s power system structure. It also portrays a reasonable picture about the different challenges that are confronted by the present day smart grid archi tectures used in transmission framework. This paper presents a unique vision for the development of smart power grids. This paper addresses major issues in smart grid. A Multiprocessor System on Chip (MPSoC) is designed to specifically meet the niche requirements of modern power system processing elements. The existing power grid model does not provide real-time information of transmission devices during emergency events. In this paper the significance of restructuring the existing smart grid architecture using MPSoC with power system components. An embedded intelligence is inserted into the power-electronics to facilitate the reconfiguration of the system, and thereby ensuring security. As the system is designed with MPSoC modified smart grid architecture, the computational complexity of the proposed system architecture significantly improving the performance of the smart grid. This paper reveals the fault tolerant methodology using MPSoC with self-diagnosis, which is essential for enhancing the proposed architecture for smart grid functionalities. Using application-specific instructions for Heterogeneous MPSoC allows finding a good performance/energy tradeoff. The functions will enhance the general execution regarding execution to accomplish the framework a reconfigurable and thusly the execution may be enhanced by upgrading which means edges in gadget system readiness and practicality and at last, worth reduction. This leads to reduce computational complexity of the existing architecture, latency and improves performance tradeoff.


EMIE - 2016