Abstract

In this paper K-Means clustering algorithm has been implemented. The proposed K-Means algorithm architecture is adaptable to the feature vectors with different dimensions to effectively utilize the system resources. Manhattan distance calculators which do not require multipliers are being used in the design to optimize the performance of the hardware. The division module realized for finding the new centroid in the architecture carries out the division operation in a single clock cycle, hence each iteration for finding a new centroid requires only one clock cycle irrespective of the number of input vectors / input vector dimensions. This modification to division operation reduces the time of clustering operation. The K-Means hardware is checked for its functionality using Modelsim simulator and is synthesized using Cadence RTL Compiler with 180-nm CMOS technology, and the experimental results show that the gate count and the maximum frequency are 600K and 300 MHz, respectively.