Abstract

Circuit like adders are the basic component for any of the processors like digital signal processors. An area and lower consumption efficient adder design are necessary for the high speed applications. In many operation, carry propogation through the adder is a critical section. Carry select adder (CSA) is efficient for the low power applications, produces the partial sum and carry by generating independently multiple carries. Hence, there is a chance in the CSA to reducing the power and area consumption. Conventional CSA uses the two pair of ripple carry adder (RCA) with cin =1 and cin =0 hence consumes more power. Complimentary pass transistor based CSA designed using inverter at the input side to drive the gate of MOS transistors and to strengthen the signal at the output side therefore it’s not an area efficient. The proposed adder uses the true single phase clock (TSPC) D-Flip flop instead of using RCA and BEC in the conventional method. This saves a significant power and area with reduced number of transistors. The 16-bit adder design is implemented in semi custom 180-nm technologies which save 75% and 25% of the power over the conventional adder and normal TSPC based adder respectively. The proposed adder is good for the power delay product which reduced to 75% and 50% over the conventional based RCA and normal TSPC adder respectively.