Abstract

Sub-threshold is a new paradigm in the digital VLSI design today. Circuits which operate in the sub-threshold region use a supply voltage that is close to or less than the threshold voltages of the transistors, so that there is a significant reduction in both dynamic and static power consumption. Leakage currents have become important sources of power consumption in modern nano scale CMOS integrated circuits. This paper acquaint with new logic family called dual mode logic, designed to operate in sub threshold region. The proposed DML logic topologies can be switched between static and dynamic modes of operation based on the system requirements. It allows operation in two modes (Dual mode), very fast in the dynamic mode while energy efficient in the static mode. This can be achieved with a simple design principle. Overall power consumption can be reduced by using sub threshold operating region. Power consumption of DML based gates are compared with conventional gates. The tanner EDA tool briefly discusses simulation results.