Abstract

The implementation of high throughout low-density parity-check\n(LDPC) code decoder with good error performance is a herculean task due to\nhigher hardware and interconnection complexity. In this paper, we present two\nfully-parallel LDPC decoder designs based on projective geometry (PG)\nstructure, PG(2,GF(23)) and iterative sum-product decoding algorithm (SPA) of\nLDPC codes. These two implementations differ in their bit-node (BN)\narchitecture. Parallel processing and fixed-point, 9-bit quantization scheme is\nused to achieve better error performance, faster convergence and higher overall\nthroughput. These fully-parallel designs are implemented for 73-bit (9,9) regularstructured\nLDPC codes, on Xilinx Virtex-5 LX330T FPGA and on 0.18μm\nCMOS technology for ASIC. Synthesis and simulation observations have been\nshown in the implementation results.