Ultralow-Power Multiplier for DSP Applications

Conference: Recent Application and Trends in Modern Engineering
Author(s): Srilakshmi K, Tilak A. V. N, Srinivasa Rao K Year: 2018
Grenze ID: 02.RATME.2018.1.3 Page: 1-16

Abstract

Multiplication is a widely used arithmetic operation in most of the\napplications. Modern digital signal processors (DSPs) need high-speed\nmultipliers to simplify the processing operations like Fast Fourier Transform\n(FFT), convolution, correlation, and filtering. However, the usage of high-speed\nmultipliers will significantly contribute to the increased power dissipation of the\nDSP. Taking the operational speed and power dissipation as paramount design\nconstraints, this work mainly concentrates on the implementation of 4x4 Vedic\nmultiplier using FinFET based Efficient Charge Recovery Logic (ECRL). The\nVedic multiplication contributes to the high-speed computation; while the usage\nof FinFET based ECRL logic lowers the power dissipation. The simulation\nresults indicate up to 66% of power savings without a significant increase in\ndelay for FinFET based ECRL logic as compared to CMOS design.

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