Abstract

In plenty of real time applications of signal processing, wireless communications,\nradio communications, biomedical systems at the receiving end the signals have to be denoised\nand their “Signal to Noise Ratio (SNR)” values have to be found. In this way in many\nadvanced applications such as Cognitive radio receiver, Wireless BMI RF receiver, in many\nDigital Signal Processing systems either at the intermediary stages, or at the receiving end\nthe noise performance is very critical. For noise performance SNR is a key parameter. In\nmany of such DSP systems one of the most efficient approaches is to have a dedicated\nhardware. Keeping in mind of the critical role of SNR, in this research we have developed\nhardware for a Novel highly efficient SNR mechanism, which is a frequency domain SNR.\nAs this Novel SNR is found to be highly efficient, and as it has never been implemented in\nhardware we have got motivated towards implementing this SNR mechanism onto Xilinx\nField Programmable Gate Arrays, specifically to find its speed of operation and\ncompatibility for the current ongoing technologies. So, as a first step we developed\nhardware for 64 sampled data and we found that the hardware is working at high Ghz rates\nand compatible for all current real time technologies in terms of sampling rates and system\nclock speeds and also useful for future technologies. As much of the current technologies use\n1024 sampled data, so secondly we have extended this hardware for 1024 sampled signals.\nWe have developed original parallel architectures for this SNR hardware implementation\nfor 1024 sampled signals. We found some Novel results and in this paper we are presenting\nthe implementation results of the parallel architectures for 1024 sampled signals and\ncomparing them with that of 64 sampled signals in terms of speed of operation and power\nutilization. The parallel architectures developed are found to be highly efficient even in the\ncase of 1024 sampled signals also, this hardware is working at high Ghz rates, but slower\nthan 64 point hardware, and also compatible for future technologies. We did this\nimplementation on Xilinx Artix-7 FPGAs using Xilinx Vivado 2015.2 Design suite. Verilog\nHardware Description Language (HDL) is used for programming this hardware.