Abstract

In this paper a Level shifter is design to mitigate power consumption in System-on-Chips (SoCs) by applying\nproper technique to reduces additional power consumption and propagation delay in the circuit. Carbon Nano-tube material\nhave one of the best property that provides variable Threshold Voltage (􀜸􀯍􀯁 ) to change 􀜸􀯍􀯁 of both PMOS Pull Up Network\n(PUN) and NMOS Pull Down Network (PDN) of transistor. In this research paper, the power and speed of CNT-FET based\nlevel shifters at 32-nm technology is calculated. It can increase the overall performance of the circuit by optimising the\nparameter like chirality, diameter, number of nanotubes and substrate (back gate) bias for both feedback-based and multi-VTH\nbased level shifters. Proposed circuit provides amplification of signal by applying input 0.2V and shifts the level to 0.9V\nwithout degradation of logic level of the signal. By applying back gate bias, minimum PDP is obtained by SI-LS i.e. 0.0028aJ\nwhich is thelowest PDP among all CMOS and FinFET technology.