Implementation of AMBA-APB Protocol with Low PowerDissipation

Conference: Recent Trends in Information Processing, Computing, Electrical and Electronics
Author(s): Sandeep Jagre, Neelesh Gupta, Nishi Pandey Year: 2017
Grenze ID: 02.IPCEE.2017.1.105_1 Page: 263-266

Abstract

The aim of the dissertation is to put in force AMBA-APB(Advance Microcontroller Bus Architecture-Advance\nPeripheral Bus) Bridge for low power dissipation. For this, simulation and synthesis of the complex bridge interface is\ndesigned which could offer minimum electrical power strength consumption and high frequency band width among AMBA\nhigh performance or speedy or high velocity buses like ASB and low active APB buses. For designing any type of ic three\nmain criteria’s are speed ,power and area. Clock is a first-rate situation in designing of any digital sequential gadget. Clock\nskew is generated when the distinction in clock signal arriving time between two adjacent register. One of the strategies to\nlimit clock skew is master slave flip-flop. So in this dissertation work we used flip-flop as a memory element with master\nslave concept which is based on the finite state machine. Advanced Peripheral Bridge with clock skew reduction technique is\nenforced within the thesis the usage of verilog HDL. For the simulation and synthesis motive, design usage summary and\npower details Xilinx’s-ISE design suite, model 14.1 has been used. Power record is added for developing better know-how of\nthe energy utilization in any gadget. The power document offers the electricity consumption precise. Hence, the whole clocks\nenergy intake is of 0.35 mW, general hierarchy strength consumption of 0.13 mW and general on chip logical strength\nconsumption of 0.040 W had been extracted from Xilinx X-Power analyzer device when APB Bridge is designed beneath the\nproposed design technique.

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