Abstract

Clean ECG (Electrocardiogram) is very important to detect many diseases. ECG signal can be corrupted by\nvarious noises in real time situations. ECG is mainly corrupted by Baseline wander noise, Powerline Interference noise, and\nEMG noise. These types of noise are present at different frequency range of ECG signal. There are various filtering\ntechniques available for removing these noises. This paper proposes FPGA based implementation of Kaiser Window based\nCascaded FIR (Finite Impulse Response) filter in which FIR High Pass Filter, FIR Band Stop Filter and FIR Low Pass Filter\nare cascaded. Proposed implementation can remove Baseline wander noise, Powerline Interference noise, EMG\n(Electromyogram) noise in a single stage. The ECG database has been taken from Physio.net. The proposed FIR filter has\nbeen synthesized and implemented on Virtex5 FPGA using Xilinx ISE 14.5.