Abstract

Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand\nof high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder\nperformance. In spite of complexity involved in floating point arithmetic, its implementation is\nincreasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs\nhave been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs\nhigh speed IEEE 754 floating point multiplier using carry select adder (CSA). Here we are introduced two carry select\nbased design. These designs are implementation Xilinx Vertex device family.