FPGA Execution of USB Transceiver Macrocell Interface with USB 2.0 Particulars

Conference: McGraw-Hill International Conference on Signal, Image Processing Communication and Automation
Author(s): C Vinod Kumar, Naveen Kumar M Year: 2017
Grenze ID: 02.MH-ICSIPCA.2017.1.47 Page: 300-306

Abstract

The universal serial bus (USB) gadgets are designed using application specific integrated circuits (ASIC)\ninnovation with implanted USB 2.0 support. Universal serial bus transceiver macro cell interface (UTMI) is a bi-directional\nserial transport interface between USB gadgets through two wire information lines (D+ and D-). The USB 2.0 particulars\ncharacterize three sorts of UTMI execution relying on their information exchange rate. Those are low speed (LS) 1.5 MHz\nonly, full speed (FS) 12 MHz only, and high speed (HS) 480 MHz/full speed (FS) 12 MHz. To handle data recovery in\nvendors Verilog code, the operating frequency should be low for full speed devices. The transmitting section of the UTMI\nsends information to various USB gadgets through information lines while receiving section of the UTMI gets information on\nsimilar information lines. The field programmable gate arrays (FPGA) execution of UTMI with HS/FS information\ntransmission rate giving USB 2.0 details. The UTMI block is outlined utilizing Verilog code and it is incorporated, simulated,\nprogrammed to the Spartan 6 group of FPGA.

<< BACK

MH-ICSIPCA - 2017