Abstract

The Successive approximation ADC is best suitable for low power applications with moderate speed and simple\ndesign. This project describes the design of SAR architecture ADC with 4-bit resolution and clock frequency ranging from\n20MHz to 1GHz. The architecture mainly consists of 4 blocks Sample and Hold (S/H) circuit, SAR Logic block, DAC and\ncomparator. S/H circuit is used to hold the signal until the conversion is completed. In this project it is implemented using\ntransmission gates and MIM capacitor. Comparator used in this project is an auto zeroed capacitor comparator, used to\ncompare the analog input signal with the reference voltage generated by DAC. DAC, used her is R-2R DAC, which converts\noutput from SAR Logic into analog signal. SAR Logic Block initially approximates the digital output and then corrects the\noutput based on comparator output. Here each individual blocks are simulated separately using Cadence tool in CMOS 45nm\ntechnology. At the top level all the blocks are integrated and simulated with power supply of 1.1V. Power dissipation from\nthe circuit is 0.108mW.